The present invention relates to a MIS capacitor having a so-called MIS structure (Metal-Insulator-Semiconductor), and to a semiconductor device on which mounted are such a MIS capacitor and a MIS transistor. More particularly, the present invention relates to measures for improving such a MIS capacitor in characteristics and for simplifying the production of such a semiconductor device.
As disclosed in U.S. Pat. No. 4,720,467 for example, there is known a MIS capacitor comprising an insulator layer formed on a semiconductor substrate, a polysilicon electrode on the insulator layer and an impurity diffusion area formed on that surface area of the semiconductor substrate which is located at a lateral side of the polysilicon electrode. More specifically, the polysilicon electrode serves as one electrode of the MIS capacitor, the impurity diffusion area serves as the other electrode of the MIS capacitor, and the insulator layer serves as an electric charge accumulating member.
There is also known an example of a capacitor having another structure in which two polysilicon layers are used. Such a capacitor is arranged such that an interlaminar insulator layer having a thickness of tens nm is interposed between two polysilicon layers, and that the polysilicon layers serve as two opposite electrodes and the interlaminar insulator layer serves as an electric charge accumulating member.
There is also known an example of a capacitor having still another structure in which two metal layers and one polysilicon layer are used. More specifically, there are formed, on a semiconductor substrate, two metal layers by and between which a polysilicon layer is held, and an insulator layer having a thickness of hundreds nm is interposed between the polysilicon layer and each metal layer.